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january 2000 1/83 AN1154 application note 8031 / m88 flash+psd design tutorial this tutorial takes you step-by-step through the development cycle of a m88x3fxx based design, from design entry, to programming the device. the first part of this tutorial shows how a m8813f1x can be used in conjunction with a handful of other ics to implement an automatic gain control (agc) design. the tutorial also shows how this design would be implemented using a discrete part solution, and appendix e summarizes the various benefits of using a m88x3fxx device over the discrete solution. the members of the m88 flash+psd family of programmable system devices are flash-based peripherals for use with embedded microcontrollers (mcus), and are in-system-programmable (isp). these psds are designed to interface easily with a variety of 8-bit mcus, and to provide them with memory, logic, and i/o. embedded designs are typically bound by cost, size, and power consumption. the market for products using embedded mcus is extremely competitive. time-to-market and quality features-per-dollar define success. in using a m88 flash+psd device, you will reduce your cost, time-to-market, power consumption, board space, design complexity, and chip count. as you read this document, you will learn how the m88 flash+psd can enhance your mcu, and meet its needs for flash memory, eeprom, sram, configurable i/o pins, programmable logic (both sequential and combinatorial), decoded address space, address expansion, backup power, code integrity, code security, and isp. all of these features are to be found in one cost-effective m8813f1x device, and allow the use of a low cost, minimal feature, rom-less mcu device. in addition to giving a step-by-step design entry tutorial, this document usefully highlights three aspects of the m88 flash+psd solution: C isp using concurrent memory or jtag Cmicro ? cell technology C the logic simulation capabilities of psdsilosiii a typical mcu design with flash memory consists of: n an mcu n the main flash memory n and C a boot prom or sram to implement an isp download to the main flash memory C over an uart channel, or some other communication link. for systems that use sram for isp, the flash-programming algorithm must first be downloaded to sram and then the mcu executes from sram during isp. any power interruption or system glitches that occur will corrupt the system. therefore, a boot prom is a necessity for applications that demand high system reliability. however, a boot prom adds cost to the system, and is difficult to update once in service. flash- based psds address these concerns and combine all of the elements necessary to enable the mcu to download easily to main flash memory, and boot memory, while in-system.
AN1154 - application note 2/83 the isp method just described requires mcu participation. the m88 flash+psd also offers another isp method, which uses a jtag interface, and requires no mcu participation. this means that a completely blank psd can be soldered into place, and the entire chip can be programmed, in-system, using sts jtag flashlink cable and psdsoft development software. this is a powerful new feature of the m88 flash+psd that allows for easy updates in the field. typically, adding a peripheral to the mcu memory space involves adding a lot of circuitry to decode the address lines, to latch the data lines, and to handle the bus timing. if an m88 flash+psd device is used, the mcu address, data, and control signals are already routed and processed inside the psd, and so this hardware overhead is not required. micro ? cells take advantage of this, and allow the designer to build logic peripherals inside the psd in an efficient and flexible manner. this tutorial compares a psd micro ? cell design with an equivalent functional design using an altera epm7064s cpld device, thereby emphasizing the efficiency of the psd approach. the m88x3fxx has 16 output micro ? cells (omcs) and 24 input micro ? cells (imcs). each micro ? cell occupies a memory location in the mcu address space, and is connected to the data bus. the ability to load the flip-flops in the omcs, and to read them back, is useful in such applications as loadable counters, shift registers, and other system logic. the imcs can latch external inputs, and be read by the microcontroller. imcs are also useful when implementing handshake communication logic with an outside source. st provides complete chip-level verilog-hdl models of all psd devices for use with the psdsilosiii simulator. these models can be used in conjunction with a user-defined stimulus file to simulate the functionality of the psd. psdsilosiii also comes with a waveform editor/viewer and watch window (for stepping through the simulation) that are used in conjunction with the stimulus file. most of the psds status and control signals, as well as all the user-defined logic in the cpld, are available for use with the waveform editor/viewer and the watch window. thus, the user can define mcu-level tasks, such as read and write, that can be used as external chip-level stimuli to the psd, and the results of the stimuli can be viewed using the waveform editor/viewer and watch window of psdsilosiii. a new utility is featured in psdsoft version 5.x. this utility automatically generates ansi-c code for the psd functions, and can be used with the users choice of mcu cross-compilers. design example the design that has been chosen, by way of an example, in figure 1, is a piece of hardware with closed- loop automatic gain control (agc). this has an analog rf receiver section, which has a programmable gain amplifier (pga) to control the signal level that is output though an envelope detection circuit. the pga gain must be adjusted in real-time to keep a constant signal level at the envelope detection output. an analog-to-digital converter (adc) monitors this output. when the agc function works properly, a constant signal level is output from the receiver, which can be used by other analog and digital circuitry for signal processing.
3/83 AN1154 - application note figure 1. block diagram of automatic gain control circuit the mcu could be used to perform this real-time gain adjustment, but this would leave it with little execution time for other tasks. it is highly desirable to free up the mcu by off-loading these repetitive tasks to dedicated hardware. the agc function can be moved into the state machine, implemented using programmable logic, as shown in figure 1. in this configuration, the mcu first loads the state machine with a desired signal level, and starts it running, and then gets on with other tasks. most of the time, the state machine works autonomously, reading the outputs of the adc and comparing the measured value with the desired value. the state machine only needs to interrupt the mcu when the signal has drifted from the desired level. along with the interrupt line, it provides two signals: trim and boost. if the signal level from the receiver is too high, the interrupt is accompanied by trim, and the mcu writes the appropriate value to the pga to decrement the gain. likewise, if the signal level is too low, the interrupt from the state machine is accompanied by boost. this tutorial shows how to implement this agc function two different ways: a discrete ic solution (using individual ic devices for programmable logic, memory, etc.), as shown in figure 2, and an integrated psd solution, as shown in figure 3. in addition to the agc function, other features that have been implemented include: the real-time-clock (rtc), in-system programmability (isp), and miscellaneous i/o signals. please refer to appendix f for information related to system memory mapping, isp issues using a uart, and memory paging considerations. ai03141 rf receiver pre- amp lo filter pga env out amplifier gain control setting 4 closed loop agc a/d converter base band signal envelope out state machine desired level 4 interrupt boost trim modulated rf signal in 80c31 mcu 4 of 8
AN1154 - application note 4/83 figure 2. block diagram for the discrete solution ai03139 vcc vcc vcc vcc a6 a6 a5 a7 a5 a7 a6 a7 a5 a3 a4 a0 a4 a0 a2 a2 a1 a3 a3 a1 a1 a2 a0 a4 fla sh_cs/ fla sh_cs/ eeprom_a 13 eeprom_cs/ eeprom_a 14 fl a s h_a 15 fla sh_a 15 eeprom_o e/ a10 a10 a8 a8 a12 a12 a13 a13 a0 a1 a2 a3 a4 a5 a6 a7 a9 a9 a11 a11 fl a s h_a 14 fla sh_a 14 fl a s h_a 16 fla sh_a 16 fla sh_oe/ fla sh_oe/ eeprom_a 13 eeprom_a 14 eeprom_o e/ eeprom_cs/ tck tms tdi tdo tdo tdi tms tck adc_out4 adc_out5 adc_out6 adc_out7 pg a _ d in 0 p g a _ d i n 0 p g a _ d i n 1 pg a _ d in 1 pg a _ d in 2 p g a _ d i n 2 env elope_out sys clock a12 a8 a9 a9 agc_intr/ wr/ psen/ ps en/ a11 a10 a10 a9 wr/ trim a12 a12 trim w r / a8 a13 a13 a9 txd a10 a14 a14 ale ale rx d txd rd/ wr/ boost a11 a11 a15 a15 boost a8 a8 rx d rd/ rd/ wr/ sra m_v c c a0 a1 a2 a3 a4 wr/ rd/ rtc_cs/ rtc_cs/ ad4 ad4 ad3 ad6 ad6 ad6 ad3 ad3 ad0 ad2 ad0 ad5 ad1 ad6 ad6 ad5 ad5 ad1 ad6 ad0 ad0 ad1 ad2 ad5 ad2 ad2 ad3 ad0 ad1 ad3 ad0 ad1 ad3 ad7 ad5 ad5 ad2 ad7 ad7 ad4 ad4 ad7 ad4 ad2 ad4 ad7 ad7 ad1 wr/ sram_cs/ sra m_cs/ sra m_oe/ sram_oe/ control0 control1 control2 agc_int/ rtc_intr/ rtc_intr/ res et/ vcc res et/ a d c _ o u t 4 a d c _ o u t 5 a d c _ o u t 6 a d c _ o u t 7 gnd conv_sta rt/ g n d gnd g n d c o n v _ s t a r t / g n d q2 2 1 3 q1 2 1 3 u9 a 7414 1 2 + - u10 co mp ara to r 4 5 1 u3 29f010 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 13 14 15 17 18 19 20 21 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 ce oe we dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u6 lh5116 8 7 6 5 4 3 2 1 23 22 18 21 20 9 10 11 13 14 15 16 17 2 4 19 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 ce we oe i/o1 1/02 i/o3 i/o4 1/ o5 1/ o6 i/o7 i/o8 v c c a10 j1 hea der 5x2 1 2 3 4 5 6 7 8 9 10 32.768 khz antenna u7 v i n d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 r d c o n v s t a r t c s u1 80c31 31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 ea / v p x1 x2 res et int0 int1 t0 t1 p1 . 0 p1 . 1 p1 . 2 p1 . 3 p1 . 4 p1 . 5 p1 . 6 p1 . 7 p0 . 0 p0 . 1 p0 . 2 p0 . 3 p0 . 4 p0 . 5 p0 . 6 p0 . 7 p2 . 0 p2 . 1 p2 . 2 p2 . 3 p2 . 4 p2 . 5 p2 . 6 p2 . 7 rd wr psen ale/p tx d rx d u5 dp8572a 4 5 6 7 8 1 2 15 16 17 18 19 20 21 22 3 14 a0 a1 a2 a3 a4 o s c _ i n cs rd do d1 d2 d3 d4 d5 d6 d7 wr o s c _ o u t intr u4 a t28c256 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 27 22 20 11 12 13 15 16 17 18 19 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 we oe ce i/o0 1/01 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 3. 6 v s1 u9 b 7414 3 4 pga u8 (receiver) a 0 c s vout a 1 a 2 w r vin u2 epm7064s 4 5 6 8 9 11 12 16 17 18 22 20 21 23 14 24 25 27 28 29 62 33 34 36 37 71 41 84 83 10 15 30 35 44 45 46 48 49 50 51 52 54 55 56 57 58 60 63 61 65 67 1 73 72 70 69 68 64 75 74 2 76 79 80 81 31 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o tms tdi i/o i/o i/o i/o i/o tck i/o i/o i/o i/o tdo i/o i/o e1 i/g cl k1 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/g cl r i/o i/o i/o i/o i/o i/o i/o i/o i/oe2/gclk2 i/o i/o i/o i/o i/o cont rol2 cont rol0 cont rol1 sy st em cloc k 128k x 8 flash 2k x 8 sram lithium battery + 32k x 8 eeprom 16 mhz with debounce pushbutton reset adc rs232 port pre- amp lo envelope detector filter jtag connector cpld mcu rtc
5/83 AN1154 - application note this is an 80c31 mcu application that has a 128k x 8 flash memory, a 2k x 8 battery-backed sram, a 32k x 8 eeprom, a real-time clock (rtc), an 8-bit analog-to-digital converter (adc), a jtag interface, an epm7064s isp cpld, and an analog receiver circuit (including pga). in the discrete solution, in figure 2, four extra ic devices are required. in the m8813f1x solution, in figure 3, the flash memory, eeprom, sram, cpld, and battery backup circuitry are all combined in the m8813f1x device. the following notes can be made regarding the discrete solution (figure 2): n the 80c31 mcu is using external memory since internal program and data storage is not sufficient. as a result, port 0 and port 1 are sacrificed for address and data. n the epm7064slc84-5 cpld is needed for address decoding, control logic, implementation of a paging/segmentation scheme for the flash memory and eeprom, and interfacing to the pga and adc. please refer to appendix d for the complete design listing for u6. n the 29f010 flash memory contains 128k x 8 bits of program memory. notice that address lines a14- a16 are driven by the cpld to support the additional address space. n the a128c256 eeprom contains 32k x 8 bits of boot memory. this allows concurrent programming of the flash memory. address lines a13-a14 are driven by the cpld to support the additional address space. n the dp8572a rtc, programmable real-time clock, is used to time-stamp various data received by the mcu. n the lh5116C2k x 8 bit sram is configured with battery backup protection. n the generic 8-bit adc converts the target signal envelope into a digital value. this ic is controlled by the cpld. n the receiver circuit consists of a collection of components, including: a pre-amplifier, a mixer, a local oscillator (lo), a pga, and an envelope detector circuit. the circuit takes an rf signal from the antenna, as input, and outputs the signal envelop. n the 7414 inverter with hysteresis (u7b) is used to provide a stable reset signal to the mcu (u1). u7a is part of the battery backup circuit for the sram. n the generic opamp comparator is part of the battery backup circuit for the sram. when v cc falls below the battery voltage, the circuit switches over to powering the sram from the battery. the integrated psd design, in figure 3, can be compared to the discrete design, in figure 2. the memory (u3, u4, and u6), and the battery backup circuit (u9a and u10) of figure 2 are all incorporated into the m8813f1x (u2) of figure 3. also, all of the functions handled by the cpld (u2 of figure 2), are implemented in the psds cpld. the i/o pins are individually configured to match the functions implemented in the original design. using jtag, the entire m8813f1x device can be programmed. also, the psd jtag pins can be multiplexed with other i/o. these jtag features are beyond the capabilities of the epm7064s.
AN1154 - application note 6/83 figure 3. block diagram for the integrated psd design ai03140 vcc vcc vcc vcc vcc tdo wr/ pg a _ d in2 t m s tsta t; trim pg a _ d in0 ad3 agc_int/ psen/ psen/ g n d a d c _ o u t 7 la 3 d3 t d o tdi conv_sta rt/ a d c _ o u t 6 ad1 txd txd rd/ d1 a11 a11 a10 a10 g n d a dc_out5 rtc_cs/ ad4 ad5 control1 rtc_ int/ a14 a14 a15 a15 ad1 boost d6 clkin signal envelope p g a _ d i n 2 d4 p g a _ c s / tck; st art_conv / agc_int/ a dc_out7 terr/; boost ad6 ad2 la 1 la 0 a8 a8 r s t / wr/ wr/ w r / g n d rxd d5 a9 a9 a d c _ o u t 4 a dc_out4 a dc_out6 ad6 t c k ad5 ad4 ad0 rx d jen/ la 4 control0 p g a _ d i n 1 t d i jen/ d7 la1 ale/ t e r r / rtc_cs/ ad2 ad7 ad7 d0 la 2 la 4 a13 a13 reset tms; a gc_int/ control2 la 3 la0 pg a _ d in1 p g a _ d i n 0 j e n / t s t a t a d c _ o u t 5 ad3 ad0 rtc_int/ rd/ rd/ a12 a12 trim d2 la 2 ale reset/ g n d g n d 32.768 khz u1 80c31 31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 ea /v p x1 x2 reset int0 int1 t0 t1 p1. 0 p1. 1 p1. 2 p1. 3 p1. 4 p1. 5 p1. 6 p1. 7 p0. 0 p0. 1 p0. 2 p0. 3 p0. 4 p0. 5 p0. 6 p0. 7 p2. 0 p2. 1 p2. 2 p2. 3 p2. 4 p2. 5 p2. 6 p2. 7 rd wr ps en ale/p txd rxd u2 m8813f1x 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 29 28 27 25 24 23 22 21 7 6 5 4 3 2 52 51 46 20 19 18 17 14 13 12 11 50 47 49 48 8 9 10 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 adio15 (tms) - pc0 (tck) - pc1 (vstby ) - pc2 (tstat) - pc3 (terr) - pc4 (tdi) - pc5 (tdo) - pc6 pc7 cntl1 cntl0 cntl2 res et pd2 pd1 pd0 j1 hea der 7x2 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 u7a 7414 1 2 u3 dp8572a 4 5 6 7 8 1 2 15 16 17 18 19 20 21 22 3 14 a0 a1 a2 a3 a4 o s c _ i n cs rd do d1 d2 d3 d4 d5 d6 d7 wr o s c _ o u t intr s1 u5 v i n d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 r d c o n v s t a r t c s u7 b 7414 3 4 u4 74hc126 2 5 9 12 4 1 0 3 6 8 11 1 3 1 1a 2a 3a 4a 2 o e 3 o e 1y 2y 3y 4y 4 o e 1 o e 3.6 v battery antenna pga u6 (receiver) a 0 c s vout a 1 a 2 w r vin system_ clock control0 control1 to au dio application control2 lo rtc reset rs232 port envelope detector 16 mhz adc pre- amp filter pushbutton with debounce jta g connect or mcu
7/83 AN1154 - application note matching the functions to a m8813f1x the mapping of the functional areas, of the original design, into the m8813f1x are shown in table 1. the 80c31, running at 16 mhz, has a t aviv (time between address valid and instruction valid) of 207 ns. an m8813f1x-15 (the 150 ns part) was selected to meet the 80c31 access time requirement. table 1. discrete solution compared to the m8813f1x solution functional area design example with discrete components the matching m8813f1x function memory 128 kbyte flash memory 32 kbyte eeprom 2 kbyte sram same same same memory paging/segmentation, and control extra logic to drive the address lines, output enables, and chip selects to the flash and eeprom automatically taken care of internally by the dpld, psd page register, psd vm register, and prioritized memory access. pld/control/demux decoder (epm7064s) address latch logic in cpld various registers used to hold data or control information to be used by external devices use dpld (decoding pld) port a in latched address mode (a7-a0) use one output micro ? cell per bit for each register i/o latched data inputs and outputs on cpld combinatorial outputs on cpld mcu i/o mode feature same supervisory/jtag automatic switch to battery backup limited jtag interface with no multiplexing of the jtag port available, and no jtag isp of memory available built-in comparator automatically switches to battery power when the system voltage drops below the battery voltage on pin pc2 (v stby ) utilizes standard jtag and non-standard extensions (to speed programming); the jtag port can be multiplexed with other i/o, and the memory and logic within the psd is isp via the jtag port.
AN1154 - application note 8/83 the m88 flash+psd functional blocks the m88x3fxx provides five system-level functional blocks, and allows the user to define and configure these blocks to meet the design specification. mcu bus interface the mcu bus interface adapts the address, data, and control lines of a particular mcu to the psd. choices include multiplexed or non-multiplexed address/data bus, and the associated control/handshake signals. plds (decode for memory and registers, general logic) the dpld generates internal chip selects for the m88 flash+psd flash memory, eeprom, sram, control registers and i/o ports, peripheral i/o mode, and micro ? cells. the cpld implements general logical functions, such as state machines, shift registers, counters, and combinatorial logic. both plds are based on flash memory technology. i/o ports the m88x3fxx has four i/o ports: ports a, b, c, and d. these ports have several modes of operation and may be selected within psdsoft during design entry, or by mcu firmware at run-time. modes that are defined by psdsoft are implemented with non-volatile memory (nvm) configuration bits that cannot be altered unless the device is reprogrammed. the remaining available i/o port operational modes are determined by the mcu writing to psd control registers. please see application note an1x55 for more details. memory the m8813f1x has 128 kbytes of flash memory, 32 kbytes of eeprom, and 2 kbytes of battery-backed sram. all of these memories may operate concurrently. that is to say that, while one (or more) type of memory is being written to, erased or read, the mcu can still be fetching program code from another. these memory blocks are placed in the system address space using the psdsoft development software. the m88 flash+psd also offers some run-time features that can be used to alter the system memory map on the fly, which is useful for memory paging, and isp. jtag isc interface the m88 flash+psd family includes a jtag channel for in-system programming (isp). this isp function is an extension of the typical jtag boundary-scan function. it is an implementation of the jtag- isc (in-system configuration) specification that is becoming an industry standard. the entire psd device may be configured and programmed while soldered to the end product. the psd can be completely blank before programming because the jtag interface needs no assistance from the mcu. st has enhanced the standard four-wire ieee 1149.1 jtag interface by making available two additional handshake lines to speed the programming. the use of the jtag interface, and the two additional handshake lines, are defined using psdsoft. also, the mcu has some control over the jtag interface at run-time.
9/83 AN1154 - application note psdsoft development tools psdsoft is sts integrated system development software tool, which runs on a pc in the windows 95 and windows nt environments. psdsoft supports the configuration of the functional blocks, as described in the previous sections. psdsoft consists of the following major modules: n psdabel n psd configuration n psd fitter n psd simulator n psd programmer n c code generator the psdsoft design process for a psd devices follows the flow shown in figure 4. psdabel psdabel has mincs hdl abel engine at its core (formerly data i/o abel). the psdabel environment provides an editor to create/edit an .abl file that can be used to define chip select logic, general-purpose logic, and psd configuration parameters. template files are provided for many mcu and psd combinations. when the abl file is compiled, logic is synthesized, and files are created and passed on to the psdsoft fitting utility. psd configuration this utility is used to specify the psd mcu bus interface type, special i/o pin assignments, and particular internal psd functions. the output of this module is a .glc configuration file, which is also used by the psdsoft fitter. psd fitter psd fitter has two main functions: the fitter and the address translator. the fitter accepts input from psdabel and psd configuration, synthesizes this user logic and configuration, and fits the design to the psd silicon. the address translator process allows the user to map the mcu firmware from a cross- compiler (in intel hex or s-record format) into the nvm blocks within the psd. as a result, the mcu firmware is merged with the logic and configuration definition of the psd. the output of the address translator is an .obj file that can be used by a programmer to program the psd device. this .obj file can also be used to program an m88 flash+psd using the jtag flashlink cable. the .obj file includes chip configuration information, the pld fuse-map, and mcu firmware. psd simulator sts version of simucads silosiii simulation software provides functional chip-level simulation for psd devices. psdsoft automatically creates files for input to the simulator. these files convey relevant design information to the simulator. as a result, the user only has to create a stimulus file since all of the signals and node names are taken from the .abl file. psd programmer psd programmer is the interface to the st magicproiii?, psdpro, pep300, and flashlink programming devices. it accepts the .obj file as input, allows viewing and editing of the .obj file, and programs the psd device. c code generation this is a new feature of psdsoft that automatically generates c code functions and headers for controlling flash psd devices. these functions and headers are ansi-c compatible. the generated files (.c and .h)
AN1154 - application note 10/83 may be edited to suit the particular application, then compiled and linked with the rest of the code. afterwards, the linker output of the cross-compiler (usually in intel hex or motorola s-record format) is merged with the configuration file of the psd device in the address translate utility of psdsoft. the functions and headers provided by psdsoft, cover psd operations such as: n flash memory program and erase algorithms n eeprom program algorithms n i/o control and definition n memory management n power management. design flow this section describes the design flow of a project, from the initial entering of the design, in psdabel, to the programming of the device, and its simulation. figure 4 shows the psdsoft design flow utility. this is the first window to appear after you invoke psdsoft. by double clicking on each box, the associated process is initiated. while this is a convenient method to navigate through the steps, this tutorial shows how to step through the process using menus and tool-bars since this approach is less obvious. the section, starting on the page after next, takes you step-by-step through a tutorial design. figure 4. psdsoft design flow ai03314
11/83 AN1154 - application note psdsoft program flow the high level steps for a psd design are as follows: 1. create or open a project, after entry into psdsoft. if you are creating a new project, specify the project name, the directory path, device family, part number, and provide a small description of the design if desired. 2. select a design template ( project .abl file), and modify this template to fit your design. 3. use psdabel to edit, compile, and optimize the project .abl file. perform abel simulation if desired. to do so, you will need to create the necessary test vectors, and to place them at the end of the psdabel file. a successful psdabel compile operation generates an optimized pla file ( project .tt2) for the fitter. 4. configure the psd device using psd configuration. this generates the project .glc file for the fitter. 5. fit the design using psd fitter. the fitters input files are obtained from psdabel and psd configuration. the fitter generates the project .fob file that is passed on to the address translator. the fitter also generates two fuse-map files, project .afu and project .pfu for the simulator. after a successful fit, it is possible to skip to step 8 (simulation), if desired, since psdsilosiii can be used before or after mcu firmware is merged with the psd configuration. 6. generate the c code, if desired. edit this c code to suit your particular application. then, compile and link it with your other application c code. your cross-compiler will output an intel hex or motorola s- record file containing the firmware. 7. perform the address translation. the address translator combines the mcu firmware file and the project .fob file into a project .obj file. this project .obj file includes the mcu firmware, the fuse-map, and the configuration bits. 8. verify the design using psd simulator. chip level simulation is based on the user's verilog stimulus file ( project .stl) and fuse-map files from the fitter. you must create the project. stl file. however, psdsoft creates files to be used with the simulator that allow you to use the same names that appear in your project .abl file, and various reserved names. 9. use psdsoft to download the project .obj file to the magicproiii?, psdpro, or flashlink jtag programmer to program the device. a compatible third party programmer can also be used. contact st or a representative near you for a list of compatible programmers.
AN1154 - application note 12/83 m88 flash+psd tutorial example this section uses the tutorial design example to illustrate the steps involved in implementing the functionality discussed earlier. the files required, which were generated for the tutorial design, can be found in the \psdsoft\tutorial\tutor8xx\tutor directory. at this point, you may wish to start the psdsoft program, so that you can follow along with the tutorial example. managing the project each new project may have its own working directory, in which all the files generated by psdsoft can reside. once you specify the new project name, psdsoft passes the working directory and pertinent information to other functional modules. in the following sections, you will be guided through a full sample design process, and key windows are displayed to help you follow the example. 1. start psdsoft. the psdsoft dialog box pops up (figure 5) enquiring whether you want to open an existing project, or to create a new one. select open an existing project, and click ok . figure 5. psdsoft dialog box (if you leave psdsoft without closing the project you were working on, it will automatically reopen when you next run psdsoft. if the psdsoft dialog box does not appear, pull down the p roject menu and select o pen project ). either way, the open project dialog box appears, as shown in figure 6. figure 6. open project dialog box ai03143 ai03144
13/83 AN1154 - application note 2. click on the browse button, which brings up the open dialog box, as shown in figure 7. go to the \psdsoft\tutorial\tutor8xx\tutor directory, select the tutor8xx.ini file, and click on the o pen button (this closes the open dialog box). figure 7. open project C open dialog box 3. click on the ok button (this closes the open project dialog box). ai03145
AN1154 - application note 14/83 the psdabel file for detailed information on psdabel, and how it relates to the m88 flash+psd, please read the comments in the file tutor8xx.abl in appendix a. also, refer to sts application note an1171 and the psdsoft psdabel-hdl reference manual . for more information on the system memory map for this tutorial design, see appendix f. to open the tutor8xx.abl design file, as shown in figure 8, click on v iew- >d esign file , and click the design entry button on the tool bar, or click on design entry in the design flow window. figure 8. design file ai03146
15/83 AN1154 - application note compiling the tutor design to compile the tutor8xx.abl file, take the following steps: 1. click on the o ptions menu. this brings up the options dialog box, with the compile options tab selected. 2. click on each of the options, and read the description in the description box to get a feel for what each option will do. then set up the options, as shown in figure 9, with the standard listing selected under listing options and the retain redundancy box checked. for a better description of the various options available, please refer to the psdabelChdl reference manual . figure 9. abel compiler options 3. select the optimization options tab, and set up the options, as shown in figure 10. use default should be the only item selected. ai03147
AN1154 - application note 16/83 figure 10. abel compiler options C optimization options 4. click on the ok button when you have finished setting up the options. 5. click on compile->compile , as shown in figure 11. or, click on the compile button on the tool bar. ai03148
17/83 AN1154 - application note figure 11. compile->compile 6. the psdabel compiler generates an error file tutor8xx.err (even if no errors are present), and writes to the log file. the compiler also generates a pla output file, tutor8xx.tt2 , which is used by psdsoft for fitting, and is optimized, based on the reduction algorithm specified in the optimization options under the o ptions menu. 7. after compilation, you can display the optimized pld logic equations that will be used by the fitter by pulling down the v iew menu and selecting the compiled eq uations , as shown in figure 12. this opens the tutor8xx.eq2 file. figure 12. view->compiled equations ai03149 ai03150
AN1154 - application note 18/83 simulating your design using abel simulation you can do a very simplistic functional simulation of the blocks that make up the pld using the simulator that is included with psdabel. it is important to note that only the functions that are generated within the .abl file can be simulated using test vectors at the end of the file. for chip-level functional simulation, you must have the version of psdsoft that includes the psdsilosiii simulation software. to use the simulator that comes with psdabel, take the following steps: 1. click on the options menu, as shown in figure 13, which brings up the options dialog box. figure 13. options dialog box 2. click on the simulator options tab, and set up the window, as shown in figure 14: under format, choose table format . ensure that the x-value 0 and z-value 0 are selected in their respective boxes, and that brief trace is selected in the trace box. for the register box, select the register power- up 0 , and make sure that the use .tmv file box is not checked. 3. click on the ok button to save your changes. ai03151
19/83 AN1154 - application note figure 14. abel compiler C simulation options 4. if you select sim ulation results in the v iew menu, psdabel will automatically start the simulation process, and display the simulation results based on the logic equations and test vectors in the .abl file, as shown in figure 15. ai03152
AN1154 - application note 20/83 figure 15. simulation results psdsoft configuration the m88 flash+psd has a programmable mcu bus interface, and is able to interface directly to many microcontrollers. using psd configuration, you can specify how to interface to the mcu you have chosen for your design. you can also configure functions specific to the psd device you are using. this tutorial design is based on the intel 80c31 microcontroller, which has an 8-bit multiplexed bus with rd , wr , and psen as the control signals, and an active-high level address latch enable (ale). to perform the configuration, take the following steps: 1. pull down the psdsoft menu in the main psdsoft window and choose psd configuration , click the configuration button or click on device config in the psdsoft design flow window. a dialog box opens entitled the global configuration, as shown in figure 16. make sure the mcu bus configuration tab is selected. 2. set up the global configuration as shown in figure 16. ensure 8-bit is selected under data bus width, mux is selected under address/data mode, high is selected under address latch/strobe setup, the enable chip-select input (csi ) box is not checked, the wr , rd , psen is selected under control setting, data space is selected under flash, and program space is checked under eeprom. this arrangement for program and data space allows the mcu to boot from eeprom in the program space, and to download to flash memory in the data space, if needed. afterwards, the mcu can override this arrangement if, for example, the flash memory needs to become part of the program space. this can be done by the mcu writing the vm register. ai03153
21/83 AN1154 - application note figure 16. mcu bus configuration 3. click on the other configuration tab, as shown in figure 17, and ensure that the enable standby voltage input (pc2) box is checked under standby voltage, edge is selected under mode of loading micro ? cell by mcu, and all other boxes are unchecked. ai03154
AN1154 - application note 22/83 figure 17. other configuration 4. click on the jtag configuration tab, as shown in figure 18, and ensure that none of the boxes are checked (because checking the boxes would enable the jtag port to be operational 100% of the time). since, in this tutorial, we are multiplexing the jtag pins with other signal functions, it is desired that jtag functions only be operational when the jen signal is active (see the figure 3 schematic). enter the value abcdef12 in the user code box below. this value will be programmed into your psd device. the user code can be any value you wish (e.g. to identify end product software revisions, serial numbers, etc.). up to eight hexadecimal characters may be entered. ai03155
23/83 AN1154 - application note figure 18. jtag configuration 5. click on the sector protection tab, as shown in figure 19, and ensure that none of the boxes are checked. the appropriate sector box should only be checked if it is desired that the selected sector be write protected. these bits can be changed, later, through the jtag port or the device programmer. ai03156
AN1154 - application note 24/83 figure 19. sector protection 6. when you are finished with the global configuration settings, click on the ok button. this saves the configuration. the m88 flash+psd configuration is now completed. if you ever wish to view the configuration file, first ensure you are in configuration mode (see step 1 of this section). next, pull down the v iew menu and select configuration report , as shown in figure 20, and then select f ile->print . ai03157
25/83 AN1154 - application note figure 20. configuration report psd fitter: fitting and address translation psd fitter consists of the fitter and the address translator. the fitter accepts input from psdabel and psd configuration, synthesizes the user logic and configuration, and fits the design to the m88 flash+psd silicon. the address translator process allows the user to map the mcu firmware from a cross-compiler (in intel hex or s-record format) into the nvm blocks within the psd. as a result, the mcu firmware is merged with the logic and configuration definition of the psd. the output of the address translator is the tutor8xx . obj file. fitting the design the input files to the fitter are: n tutor8xx.tt2C pla file generated by psdabel. n tutor8xx.glcC m88 flash+psd configuration file generated by psd configuration. the output files generated by the fitter are: n tutor8xx.fobC pld fuse-map and m88 flash+psd configuration file. n tutor8xx.afuC generated for use by the simulator. n tutor8xx.pfuC generated for use by the simulator. n tutor8xx.objC object file (pld and configuration portion only). n tutor8xx.frpC fitter report file. to fit a design: 1. click on the options menu, and select the fitter options tab to specify one of the four fitting options, as shown in figure 21. for the tutorial, choose keep current under pin assignment, and ensure that the enable product term expansion and perform register synthesis boxes are checked. ai03158
AN1154 - application note 26/83 figure 21. fitter options 2. click ok to save the fitter options. then, pull down the psdsoft menu in the psdsoft window and choose psd f itter , as shown in figure 22, or click on the logic synthesis and fitting box in the psdsoft design flow window. ai03159
27/83 AN1154 - application note figure 22. psdsoft->psd fitter 3. pull down the fitter menu and choose fitting , as shown in figure 23, or click the fit button on the tool bar. if you had clicked on the logic synthesis and fitting box in the design flow, the fitter would run automatically, and this step would not be necessary. figure 23. fitter->fitting 4. the fitter appends to two files: the log file ( psdsoft.log ) and the error file ( tutor8xx.err ). check the log file for any possible errors. if there are no errors present (there should not be if you did not modify the tutor8xx.abl file), skip to step 7. 5. if the fitting is not successful, you may have to view the tutor8xx.eq2 file in psdabel to see which logic function caused the fitting problem, and to modify the tutor8xx.abl file accordingly. to view the optimized equation file ( tutor8xx.eq2 ), see step 7 in the section entitled compiling the tutor design on page 15. ai03160 ai03161
AN1154 - application note 28/83 6. re-compile the modified tutor8xx.abl file. repeat steps 3 to 6 until a successful fit has been found. re-enter the fitter program, and proceed to step 7. 7. examine the fitter report file by pulling down the view menu, as shown in figure 24. the report file shows the results of the fitting process, and the pin assignment for the m88x3fxx. if you want a fitting other than the one generated, return to the tutor8xx.abl file to change the signal and pin assignments as appropriate. figure 24. view->fitter report generating c code psdsoft can generate ansi c code functions and headers for controlling the m88 flash+psd. this is an optional step. however, it will save you time by implementing low-level psd driver function and header files. the functions and headers are ansi-c compatible. the .c and .h files that are generated should be edited to suit your application, then compiled and linked with the rest of your application code, using an mcu cross-compiler and linker. the functions and headers that can be generated by psdsoft include the following operations: n flash memory program and erase algorithms n eeprom program algorithms n i/o control and definition n memory and power management. although c code generation can be performed anytime after a project is opened, we recommend it be done after you have successfully performed the fit of your design. once a successful fit is achieved, all pin functions and psd configurations are defined, and the c code may be tailored accordingly. the source c programming files to implement the agc function for this tutorial have not been provided. since this tutorial is meant to cover all aspects of a m88 flash+psd design, though, we cover a description of how you would use the c code generation utility for your own project. take the following steps to generate c code: 1. pull down the tools menu in the psdsoft window and choose generate c code , as shown in figure ai03162
29/83 AN1154 - application note 25. alternately, click the c code gen button in the design flow window. figure 25. tools->generate c code the dialog box should appear, as shown in figure 26. figure 26. c code generation C functions/headers the functions/headers dialog box has the following sections: C device info : this contains the m88 flash+psd family and part number of the current project. these values cannot be changed unless this project is closed and a different one is opened. C header : this is for specifying the folder in which you would like to place the c header files (.h) generated by psdsoft. (click the browse button to help in filling in this section). typically, a folder in your mcu cross-compiler environment is chosen. you cannot change the name of the headers ai03163 ai03164
AN1154 - application note 30/83 file(s) at this point since these header files may referenced by name within other header files or the c functions that are also generated by psdsoft. once all of the headers and functions are copied to their designated folders, you may edit the header file names any way you wish, as long as you change their names in the respective #include statements. C functions : this is for specifying the folder in which you would like to place the c function file (.c). (click the browse button to help in filling in this section). typically, a folder in your mcu cross- compiler environment is chosen. this file will contain the functions you specify in the next section. C c code selection : select the categories of c code functions that you would like to integrate into your c application program. under psd category are the major psd functional groups that are supported with c code for the psd device that is used for this project. under c code coverage is a brief list of the individual functions that are available within each category. to select more than one category, hold the ctrl key while making selections with the left mouse button. even if more than one category is selected, though, only one .c file is generated because functions are appended within the same file. C description : this offers a description of the functions that are generated if selected in the c code selection box. if you double-click on a function within the description box, the c code that will be generated is shown, so you can get an idea of what will appear in the sample c file. 2. after you have made your selection, first click apply , then click ok . in this example, three files will be written to your folder(s), which are: C m8813f1.c: the ansi-c source for all of the selected functions C m8813f1.h: the ansi-c header file to define particular psd registers C map813f1.h: the ansi-c header file to define locations of system memory elements (flash, eeprom, psd registers, etc.). the m8813f1.h file contains define statements for each individual c function within the m8813f1.c file. later, edit m8813f1.h, and simply remove the comment delimiters (//) from the define statement for any c function that you would like to be compiled with the rest of your c source code. 3. click on the coded examples tab at the top of the dialog box, as shown in figure 27.
31/83 AN1154 - application note figure 27. c code generation C coded examples this sheet contains several examples that you may use as a basis for building your own c code application. these are complete projects (main, functions, and headers) targeted at a particular mcu. you may copy these files to another folder, to browse them for ideas, or cut and paste sections from the examples into your own cross-compiler environment. there are three sections: C example: to specify the folder in which you would like to place the example project files generated by psdsoft. (click the browse button, and select a folder, when filling in this section). C example selection: there are several areas for which you may generate c code. each category implements a high-level system function, such as memory paging, uart downloads to flash memory, etc. C description: this describes each of the coded examples in the example section once the c code generated by psdsoft is integrated into your own c application, and is successfully compiled and linked by your mcu cross-compiler, you are ready for address translation. performing the address translation the address translator combines the tutor8xx.fob file with the mcu firmware file(s) generated by your chosen mcu cross-compiler. address translator generates the tutor8xx.obj file that is to be downloaded to a programmer that is compatible with the m88 flash+psd. the addresses within in the generated tutor8xx.obj file are special direct addresses C meaningful to a programming device. they are not system addresses, that an mcu would use, or that the dpld decodes. that is what is meant by address translate. it is a translation of system addresses that the ai03165
AN1154 - application note 32/83 mcu and its compiler/linker knows about, to a set of direct addresses that a device programmer knows about. to perform the address translation, take the following steps: 1. pull down the psdsoft menu, and choose psd fitter . then, pull down the fitter menu and choose address translate , or select mcu code mapping in the design flow. the address translation dialog box appears, as shown in figure 28. figure 28. address translation you will notice a warning message from psdsoft upon entering the address translate window. this warning is a reminder to ensure that you take paging into account when entering the start/stop addresses and file names. the address translation dialog box has the following sections: C memory select name: this is the name of the psd memory segment that will be selected when the associated equation is true. C memory select equations: each cell shows the equation for the appropriate psd memory segment. these are the optimized equations from the psdabel file. they are displayed for convenience, and cannot be modified in this window. C file address start: this is the first mcu system address, from mcu compiler/linker, that will be mapped to a psd memory segment. C file address stop: this is the last mcu system address, from mcu compiler/linker, that will be mapped to a psd memory segment. C file name: this is the mcu firmware file that is generated by your mcu compiler/linker. C record type: the supported formats are intel hex or motorola s-record. C mapping mode: two modes of mapping are supported, direct and relative. for more information, please consult the psdsoft user manual . notice that psdsoft attempts to fill in the file start and file stop addresses based on your psdabel equations. however, if paging is used, as in this tutorial, these file addresses must be handled carefully since psdsoft does not know how your mcu cross-compiler and linker handles paging. as we progress, this process should become clear. ai03166
33/83 AN1154 - application note 2. type in the file names of your mcu linker output in the appropriate places. in this example, five files are used. (see appendix f for information on the system memory map and how these files relate.) four of the five files are to be programmed into flash memory on different pages. the remaining file is to be programmed into the boot area of the eeprom. the four flash files are page_0.hex, page_1.hex, page_2.hex , and common.hex . the file for the eeprom is boot.hex . each of these files can contain up to 32 kbytes of code. 3. enter the file start addresses, file stop addresses, and file names according to table 2. table 2. mapping the memory sectors to files in this design, a different file name has been used for each of the sections of code in the flash memory. this is because of the address space overlap of the segments. this file scheme is used because, even though these sections of code physically reside on different memory pages, some linkers will place them in overlapping absolute address space. the method you use depends on your linker. alternatively, you can use a single file name across many memory chip selects if your linker automatically appends extra address bits that represent your paging scheme. you would then, for example, enter 18-bit addresses to accompany the single file name, which is passed to the address translate utility, instead of 16-bit addresses to accompany several file names. optionally, you can specify only the eeprom contents to be programmed by the device programmer. it may be desired to load system code into flash memory while it is in-system, not on a device programmer. in this case, only information for ees0 and ees1 should be entered in the address translate utility. 1. ensure that direct mapping is selected in the mapping mode box. 2. select intel hex record in the record type box. 3. click on ok to perform the address translation. if no errors are indicated, then tutor8xx.obj will be placed in your project directory. if your copy of psdsoft includes the psdsilosiii simulator, you should simulate and verify your design before programming the m88 flash+psd. please see the next section on how to simulate the tutorial design. memory select file start address file stop address file name fs0 0000 3fff common.hex fs1 4000 7fff common.hex fs2 8000 bfff page_0.hex fs3 c000 ffff page_0.hex fs4 8000 bfff page_1.hex fs5 c000 ffff page_1.hex fs6 8000 bfff page_2.hex fs7 c000 ffff page_2.hex ees0 0000 1fff boot.hex ees1 2000 3fff boot.hex ees2 - - - ees3 - - -
AN1154 - application note 34/83 m88 flash+psd chip simulation psdsilosiii is st's version of simucads silosiii simulator software. it provides chip-level simulation and design verification using the verilog hardware description language (verilog-hdl). appendix b lists the stimulus file ( tutor8xx.stl ) for this tutorial. many of the internal nodes on the m88x3fxx are available for tracing. descriptions of the signals that can be traced by the simulator are listed in appendix c. psdsoft generates all but one of the input files required by the simulator. the file that must be created is the stimulus file (.stl). in the stimulus file, you can use the same names you used in your psdabel file, and the predefined ones in appendix c. psdsoft.run file one of the files generated by psdsoft for the simulation process is psdsoft.run, as listed in figure 29. it is a command batch file used by psdsilosiii. for additional information on the psdsilosiii commands (those commands that start with !), please refer to psdsilosiiis on-line help. figure 29. psdsoft.run file in the psdsoft.run file: n `time-scale 1ns/0.1ns is a compiler directive for defining the delay values for a module n 1 ns is the unit of measurement for times and delays n 0.1 ns is the precision to which the delays are rounded off n `include is also a compiler directive that allows the entire contents of a verilog source file to be included in another file ( psdsoft.run in this case). tutor8xx.top is generated by psdsoft, based on the psdabel file, and allows you to use of any of the signal names within the psdabel file. there are also parameter definitions for high impedance state signals (z1 through z32) in the .top file. notice how the endmodule statement is the last statement in the psdsoft.run file. it is there because it complements the module wsidesign statement in the .top file. there is one important thing to note about the included library files: these files look for other files automatically generated by psdsoft from the fuse-map file, and have a .afu or .pfu extension. they allow simulation of the logic, defined in the .abl file, in the stimulus file. running the logic simulator 1. review the stimulus file ( tutor8xx.stl ) listed in appendix b. 2. pull down the psdsoft menu in the main psdsoft window and select psd simulator , or click the simulator button on the tool bar. 3. the tutor8xx.stl file is automatically opened in psdsoft, as shown in figure 30. !reset all !file .sav = tutor8xx !control .ext = all `timescale 1ns/0.1ns !lib d:\psdsoft\psd8.v `include "tutor8xx.top" `include "tutor8xx.stl" endmodule
35/83 AN1154 - application note figure 30. running the logic simulator 4. click on logicsim , as shown in figure 31, to invoke the psdsilosiii simulator figure 31. logicsim the following events happen automatically, as a result of clicking on the logicsim button: C the psdsilosiii simulator starts C the simulator loads the project tutor8xx.spj , psdsoft.run , and a window displaying the tutor8xx.stl file, as shown in figure 32. ai03167 ai03168
AN1154 - application note 36/83 figure 32. logic simulator input 5. click on the go button. this automatically opens an output window for viewing the results of the simulation, as shown in figure 33. figure 33. logic simulator output running the analyzer now that the logic simulation is complete, the results can be displayed with the psdsilosiii data analyzer by performing the following steps: 1. pull down the window menu and select data analyzer , as shown in figure 34; or press f6, or click on the appropriate button on the tool bar. ai03169 ai03170
37/83 AN1154 - application note figure 34. running the analyzer 2. the psdsilosiii data analyzer window appears with the simulation results displayed on screen, as shown in figure 35 (but your screen will look different .). please see the tutorial on the data analyzer and the explorer under help->contents on how to rearrange and group signals. figure 35. simulation results working with the explorer the explorer in psdsilosiii can be used in conjunction with the data analyzer to add and trace signals. to open the explorer, ensure that you have simulated the design by following the steps in the section entitled running the logic simulator, on page 34. next click on the window->open explorer menu selection or the explorer button and the explorer window will appear, as shown in figure 36. the explorer shows all viewable signals. ai03171 ai03172
AN1154 - application note 38/83 figure 36. explorer signals can be added to the data analyzer window using the explorer by holding the ctrl button down, and clicking on all the signals that you want to add to the data analyzer window. once you have chosen all the desired signals, right-click on one of the signals, and select add signals to analyzer . next, click anywhere in the data analyzer window, and the signals you added will appear at the bottom of the window, as shown in figure 37. figure 37. adding signals to the analyzer for more information on the explorer or data analyzer, please see the on-line help, and the psdsilosiii user manual . also, please refer to this manual for information on how to us the psdsilosiii watch window, which is beyond the scope of this tutorial. programming the m88 flash+psd the psd programmer is the programming interface to the st magicproiii ? , psdpro, and flashlink programmers. it enables downloading any psd .obj file; and displays the flash and eeprom locations, the pld fuse-map, and the configuration bits (acr). you can also perform the following operations from the functions menu: C blank test: to check to see if the device is blank. C upload: to upload the contents of the device that were programmed to the buffer. C program: to program the device with the .obj file. C verify: to verify the programmed device against the .obj file in the buffer. C erase: to erase the device completely. ai03173 ai03174
39/83 AN1154 - application note if you have a magicproiii, psdpro, or flashlink device programmer connected to your pc, take the following steps to program the m88 flash+psd after the design has been compiled and the .obj file has been generated: 1. pull down the psdsoft menu in the main psdsoft window and choose psd programmer , or click the appropriate button on the tool bar. 2. the tutor813xx.obj file is downloaded and displayed on the screen automatically, as shown in figure 38. figure 38. psd programmer assuming you have a magicproiii programmer installed, to program a device do the following: 1. pull down the functions menu and select program; or click the program button on the tool bar that is available when the psd programmer is invoked. the psd programmer C program confirmation dialog box appears, as shown in figure 39, which enables you to program the flash, eeprom or pld/ acr (psd configuration) regions of the device. ai03175
AN1154 - application note 40/83 figure 39. psd programmer C program confirmation 2. select all, as shown in figure 39. 3. place the psd device into the programmer, checking that it is correctly orientated, and snap the lid down on the device carrier. then, click on the ok button. as programming takes place, the magicproiii programmer checks each location, after it is programmed, to make sure it matches the contents in the .obj file. if a particular location cannot be programmed properly, an error message is shown. if this occurs, you must restart from the beginning, and program a fully erased and functional part. psdpro if you have a psdpro connected to one of your pcs parallel ports, you can select and configure it by going to the options menu in the psd programmer environment and selecting hardware setup , as shown in figure 40. figure 40. psd programmer C hardware setup once the psd programmer C hardware setup dialog box appears, select psdpro, in the hardware section, as shown in figure 41. ai03176 ai03177
41/83 AN1154 - application note figure 41. psd pro next, you will see that the auto select option becomes active. this means that psdsoft will automatically detect to which pc parallel port your psdpro is connected. just click ok , and the psdpro will be detected and configured if the connections are good. the same menu options and capabilities that apply to the magicproiii in the section above also apply to the psdpro. jtag: flashlink if you have a flashlink cable installed on one of your pcs parallel ports, you can select and configure it as follows: 1. go to the options menu in the psd programmer environment, and select hardware setup . once the psd programmer C hardware setup dialog box appears, select flashlink, in the hardware section, as shown in figure 42. figure 42. flashlink 2. next, you will see that the auto select option becomes active, as well as loop test , as shown in figure 43. ai03178 ai03179
AN1154 - application note 42/83 figure 43. auto-select and loop test auto select means that psdsoft will automatically detect to which pc parallel port your flashlink cable is connected (even if the other end of the flashlink cable is not connected to the target system). just click ok , and the flashlink cable will be detected. optionally, you can return to the hardware setup menu to run a loop test on the flashlink cable. this is a hardware integrity test that requires the loop-back cable (that is provided) to be installed on the flashlink cable. (please see the flashlink installation manual). 3. now connect the flashlink cable to your target system, and power-on the system. the target system needs to be powered up since the flashlink circuitry draws its power from the target. 4. set up your jtag chain (as described in the next section) 5. once your jtag chain has been set up, program your device while it is in-system. (programming is accomplished in the jtag chain setup window. this is described in the next section.) setting up a jtag chain this section takes you step-by-step through the creation of a jtag chain file. since this procedure has not been finalized, please check our web site (www.st.com) for updates to this document. the following rules apply for setting up a jtag chain: n a jtag chain of one to or more devices must be defined. n all jtag compatible devices that are connected to the jtag bus, including the m88 flash+psd and non-psd devices from other vendors compose a jtag chain. n non-psd devices that are part of the jtag chain will be placed, automatically, in bypass mode. n the length of the instruction register, along with a name and device id must be entered for each non- psd device. (in future versions of psdsoft, you will be able to load this information automatically with a bsdl file.) n before programming the psd device(s), the user must have a valid .obj file for each psd device in the chain n additionally, a serial vector format file, filename .svf, can be created for third party jtag programming support. please refer to application note an1153 for information in these areas: C jtag spec compliance C programming support C program/erase flow control C svf/bsdl file information C enhanced isp functions C multiplexed jtag pin functions C dedicated jtag pin functions ai03180
43/83 AN1154 - application note C st jtag isp connector C jtag chaining now, lets step through a sample jtag chain setup, and create a jtag chain file (.jcf). 1. under jtag menu, select jtag chain setup , as shown in figure 44, or click jtag prog in the design flow. figure 44. jtag chain setup this opens the jtag chain setup dialog box, as shown in figure 45. figure 45. jtag chain setup dialog box 2. in the chain information box, click browse . this brings up the open window, as shown in figure 46. select the tutor8xx.obj file in the \psdsoft\tutorial\tutor8xx\tutor\ directory, and click open . ai03181 ai03182
AN1154 - application note 44/83 figure 46. jtag chain setup C open window your jtag chain setup window should now appear as shown in figure 47. figure 47. jtag chain setup window if the device name (m8813f1x in this case) does not automatically appear in the device name window, select the appropriate device. 3. click the add button. your jtag chain setup window should appear as shown in figure 48. ai03183 ai03185
45/83 AN1154 - application note figure 48. jtag chain setup window C after an add 4. right -click anywhere on the line that just appeared (line 1), and select properties , as shown in figure 49. ai03186
AN1154 - application note 46/83 figure 49. jtag chain setup window C selecting properties 5. this opens the jtag chain setup properties dialog box. ensure that the set pins/flow control tab is selected, and set up the window with the following selections (based on figure 3 of this tutorial). the proper selections are shown in figure 50. under flow control, select option 3 . in the set pins box, set up the ports as follows: C port a: set all the pins to output low (cmos) C port b: set pins pb7 to pb3 to input (hi-z), and pins pb2 to pb0 to output low cmos) C port c: change pc3 to tstat (cmos), and pc4 to terr (cmos). leave the rest of the pins as they are. C port d: set pins pd1 and pd0 to input (hi-z), and pd2 to output high (cmos) ai03187
47/83 AN1154 - application note figure 50. jtag chain setup properties 6. click on the apply button (which saves the information you have entered, so far, and greys the apply button out). then, click on the jtag attributes tab. your jtag chain setup properties window should now appear as shown in figure 51. ai03188
AN1154 - application note 48/83 figure 51. jtag chain setup properties C jtag attributes the device name, instruction register length:, and jtag device id: are all greyed out because this information is automatically entered whenever you select a m88x3fxx device. if you want to enter information about a non-psd device, which is to be included in your chain, here is the place to do it. if you add another device, you need to enter valid information in the jtag attributes section. also, note that if you select the jtag device id box, psdsoft verifies the jtag id before programming or erasing the device. 7. click on the user code tab, to give the display shown in figure 52. if you enter a value in the user code box, the value is compared with the user code already programmed into the device before any jtag operation occurs (e.g. erase, program, etc.). if you leave this area blank, no comparison is performed. enter abcdef12 in the user code box. then press apply (which greys the apply button out), and finally press ok . ai03189
49/83 AN1154 - application note figure 52. jtag chain setup properties C user code 8. now, you should be back to the jtag chain setup window. right click on the same line as you did in step 4, only this time, choose erase , as shown in figure 53. ai03190
AN1154 - application note 50/83 figure 53. jtag chain setup erase 9. you should now see the operation: erase dialog box, as shown in figure 54. ensure that all is checked under the regions block, and click ok . figure 54. operation erase 10.your jtag chain setup window should now appear as shown in figure 55. click go to start the exchange on the flashlink cable. if the log mode box is checked, the jtag communication status will appear in the psdsoft log window, and in the file tutor8xx.log . turning on the log mode feature will slow down the jtag communications. ai03191 ai03192
51/83 AN1154 - application note figure 55. jtag chain setup C after the erase 11.after the erase has completed (as indicated in the log window), right click on the same line as in step 4, and choose program . select ok when the window, as shown in figure 56, appears. figure 56. operation program your jtag chain setup should now appear as shown in figure 57. select go , and the psd will be programmed with the information in the tutor8xx.obj file. ai03193 ai03194
AN1154 - application note 52/83 figure 57. jtag chain setup C after program 12.after you have programmed the device, click reset at the bottom of the window. this resets the target circuit board that is connected to the flashlink cable. this is needed after the flashlink programs the psd because the mcu will have lost its mind at this point. 13.click on the save button, to save your work in a jtag chain file for future use. this action brings up the save as dialog box, as shown in figure 58. type tutor8xx in the file n ame box, and click save . the file tutor8xx.jcf will be created. figure 58. jtag chain setup C save 14. now, the jtag chain setup window should appear as shown in figure 59. ai03184 ai03195
53/83 AN1154 - application note figure 59. jtag chain setup C after the save 15.if you need to load this .jcf file in the future, you will have to click on the browse button, which will bring up the open dialog box, as shown in figure 60. choose the tutor8xx.jcf file, and click open . figure 60. jtag chain setup C open dialog box lastly, before leaving the jtag chain setup window, you may wish to create a serial vector format (.svf) file for use with a third-party programmer. to do so, click the create svf button, and browse through your directory tree to find a place where you want to place the .svf file. ai03196 ai03197
AN1154 - application note 54/83 isp and the m88 flash+psd the m88 flash+psd may be programmed in-system, with or without participation from the mcu. for isp with the mcu, please see appendix f for uart download information and considerations. for isp without mcu participation, see the section entitled jtag: flashlink on page 41. for flashlink jtag programming within the psdsoft environment please see the application note, an1153 . references n m88 flash+psd family data sheet n application note an1153 for detailed use of the jtag channel n application note an1171 for details on the cpld and i/o pins n application note an1176 for a design guide for the 68hc11 and m8813f1x. n application note an1177 for a design guide for the 80c51xa and m8813f2x. n application note an1178 for a design guide for the 80c51 and m8813f2x.
55/83 AN1154 - application note appendix a: abel design file tutor8xx.abl module tutor8xx title '8xx tutorial design file'; // designed by:dan harris and mark rootz // design date:6-16-98 // description:this shows the logic implementation of the sample design in the 8xx tutorial. // the design highlights the following functionality of the m88x3fxx: // * effective and efficient use of the input and output micro<->cells // * how to use i/o pins while the underlying micro<->cell is being used for // other functionality. // * use of the wsipsd property statement to output demultiplexed address bits, // and define input micro<->cells/output micro<->cells. // * multiplexing the jtag pins with other i/o. // * how to logically interface to an 80c31 mcu, rtc, and an agc circuit. // revision:1.0 // rev date:9-21-98 // convention:the n is used throughout the file to indicate active low signals. // note that it is not used with the reserved signal names below. "************************** bus interface signal declarations ************************** // the reserved signal names are automatically assigned to the appropriate pin // the following are inputs from the mcu wr pin; "cntl0 input:(pin 47)- write strobe rd pin; "cntl1 input:(pin 50)- read strobe psen pin; "cntl2 input:(pin 49)- program store enable ale pin; "pd0 input:(pin 10)- address latch enable reset pin;"input:(pin 48)- system reset a15..a0 pin;"input:(pins 46..39,37..30)- demuxed address "************************** port a, b, c, d pin declaration ************************** // port a i/o // control outputs are mcu i/o mode outputs control0..control2pin 23, 22, 21;"some generic control signals // assign the latched/demultiplexed address to port a, pins pa4 to pa0. wsipsd property 'address_out aout[4:0]:addr_out[4:0]'; // port b i/o
AN1154 - application note 56/83 pga_din2..pga_din0pin 5, 6, 7;"data bits used to program the pga "implemented with mcu i/o mode measured_level3..measured_level0 pin istype 'reg';"upper 4 bits of the a/d converter (adc) wsipsd property 'databus_imc d[7:4]:measured_level[3:0] portb'; // port c i/o // note that pins pc0, pc1, and pc5-6 are multiplexed output/jtag signals. pc3, pc4, and pc6 // are jtag signals that are not multiplexed. // ensure that under "global configuration" with the "jtag configuration" tab selected that none // of the boxes enabling various jtag signals on certain pins are checked because the device // will expect only valid jtag signals on these pins, and no multiplexing can be done under these // circumstances. // pin pc2 (pin 18) is used for vstby (set in global configuration) intrn pin 20;"interrupt the mcu when the gain needs to be changed/jtag tms start_convpin 19;"start conversion signal for the adc/jtag tck trim pin 17;"the gain is too high and needs to be decremented/jtag tstat boost pin 14;"there is not enough gain--increment it/jtag terrn jcen pin 11;"jtag chip enable signal used to demultiplex port c output and jtag i/o // port d i/o // pd0 (pin 10) is assigned above to the ale signal from the microcontroller. // any external chip selects that are generated by decoding an address should be placed on // port d when possible to save as many resources as possible. rtccsn pin 8;"real time clock (rtc) chip select/jtag tdo clkin pin;"port d pin pd1 (pin 9) system clock // output micro<->cell assignments wsipsd property 'databus_omc d[7:4]:desired_level[3:0] mcellab'; wsipsd property 'databus_omc d7:begin_cycle mcellbc'; "************************** internal node declarations ************************** mxord3 node;"this signal is needed to save product terms meqd node;"true when the measured signal equals the desired signal level
57/83 AN1154 - application note begin_cycle node istype 'reg';"this signal takes the state machine out of idle state1..state0 node istype 'reg';"state machine bits desired_level3..desired_level0 node istype 'reg';"the desired gain level fs7..fs0 node;"main flash memory segments ees3..ees0node; "eeprom memory segments // reserved node names rs0 node;"select for the sram memory space csiop node; "control register jtagsel node 102;"this is the jtag enable product term. it is used to enable "the jtag port signals. pgr1..pgr0 node;"internal psd page register bits // the following page register bit definitions are an example of how to manipulate memory to // facilitate isp. this scheme is explained in appendix f of application note 57. swapnode 117;" this page register bit (pgr7) will be used for swapping " memory segments after a firmware download from the 8031 " uart port has completed. when swap = 0, the secondary " nvm occupies boot area for isp, swap = 1, primary nvm " occupies boot area. enable_data_half node 116; " this page register bit (pgr6) will be used to manipulate " the eeprom. the use of this bit is one way to divide the " eeprom in into two equal sections, one for boot and one for " general data. when this bit=0, the boot section is active. " when this bit = 1, the data section is active. "************************** definitions ************************** dlevel = [desired_level3..desired_level0];"desired gain level set by mcu mlevel = [measured_level3..measured_level0];"measured gain level latched by imcs state_machine = [state1..state0]; x = .x.;"don't care symbol c = .c.;"clock symbol page = [pgr1,pgr0]; address = [a15..a0];"de-muxed microcontroller address signals
AN1154 - application note 58/83 equations "************************** dpld equations ************************** // generate active high chip selects for the main flash segments. each segment is 16k bytes // for the m88x3fxx devices. fs0 = ((address >= ^h8000) & (address <= ^hbfff) & (page == 3) & !swap) # ((address >= ^h0000) & (address <= ^h3fff) & (page == x) & swap); fs1 = (address >= ^h4000) & (address <= ^h7fff) & (page == x); fs2 = (address >= ^h8000) & (address <= ^hbfff) & (page == 0); fs3 = (address >= ^hc000) & (address <= ^hffff) & (page == 0); fs4 = (address >= ^h8000) & (address <= ^hbfff) & (page == 1); fs5 = (address >= ^hc000) & (address <= ^hffff) & (page == 1); fs6 = (address >= ^h8000) & (address <= ^hbfff) & (page == 2); fs7 = (address >= ^hc000) & (address <= ^hffff) & (page == 2); // generate active high chip selects for the eeprom segments. each segment is 8k bytes for // the m8813f1x devices. ees0 = ((address >= ^h0000) & (address <= ^h1fff) & (page == x) & !swap) # ((address >= ^h8000) & (address <= ^h9fff) & (page == x) & swap & !enable_data_half); ees1 = ((address >= ^h2000) & (address <= ^h3fff) & (page == x) & !swap) # ((address >= ^ha000) & (address <= ^hbfff) & (page == x) & swap & !enable_data_half); ees2 = (address >= ^hc000) & (address <= ^hdfff) & (page == x) & swap & enable_data_half; ees3 = (address >= ^he000) & (address <= ^hffff) & (page == x) & swap & enable_data_half; //generate active high chip select for the psd sram (2k bytes). rs0 = (address >= ^h0100) & (address <= ^h08ff) & (page == x); // generate active high chip select for the psd control registers. 256 contiguous bytes must be // decoded for all m88x3fxx devices. csiop = (address >= ^h0900) & (address <= ^h09ff) & (page == x); // enable the jtag port when the jtag chip enable (jcen) signal is active
59/83 AN1154 - application note jtagsel = !jcen; "************************** gpld/ecspld equations ************************** // important note: comment these next four equations out for the abel simulation only. the // psdsilosiii simulator requires the equations (and they are functionally // correct). the problem is that the mcu presets (loads) and clears these // registers, and the value is not registered through the d input. however, // the abel simulator does not reconize any "dot" extentions (as these would // normally be set up through equations). the basic functionality can still // be properly tested, but how it is actually implemented in hardware is // slightly different. // so, if you intend to use the abel simulator, comment out the following // four lines so that the test vectors at the end of the file will work // properly. dlevel.ck = 0; dlevel := 0; begin_cycle.ck = 0; begin_cycle := 0; mxord3 = measured_level3 $ !desired_level3; // trim the gain when the measured signal level is greater than the desired signal level. // trim = mlevel > dlevel trim = (measured_level3 & !desired_level3) # ((measured_level2 & !desired_level2) & mxord3) # ((measured_level1 & !desired_level1) & mxord3 & (measured_level2 $ !desired_level2)) # ((measured_level0 & !desired_level0) & mxord3 & (measured_level2 $ !desired_level2) & (measured_level1 $ !desired_level1)); // boost the gain when the measured signal level is less than the desired one. meqd = (mlevel == dlevel); boost = !meqd & !trim; // generate the chip select !rtccsn = ((address >= ^h0a00) & (address <= ^h0aff)); // loading of the various registers
AN1154 - application note 60/83 mlevel.ld = !clkin; // state machine which controls the conversion start of the adc, the interrupt to the mcu, // and the strobing of the imcs state_machine.ck = clkin; state_machine.re = !reset; state_diagram state_machine; state 0: start_conv = 0; intrn = 1; if (begin_cycle == 1) then 1 else 0; state 1: start_conv = 1; goto 2; state 2: start_conv = 0; goto 3; state 3: !intrn = trim # boost; "interrupt when measured not equal to desired goto 0; test_vectors // test the state machine, trim, and boost signals ([clkin, reset, begin_cycle, mlevel, dlevel] -> [start_conv, intrn, state1, state0, trim, boost]) [ x, 0, x, ^h3, ^h4 ] -> [ x, x, x, x, 0, 1 ];"system in reset [ 0, 1, x, ^h4, ^h4 ] -> [ 0, 1, 0, 0, 0, 0 ];"system not in reset [ c, 1, 1, ^h5, ^h4 ] -> [ 1, 1, 0, 1, 1, 0 ]; [ c, 1, 1, ^h5, ^h4 ] -> [ 0, 1, 1, 0, 1, 0 ]; [ c, 1, 1, ^h5, ^h4 ] -> [ 0, 0, 1, 1, 1, 0 ]; [ c, 1, 1, ^h4, ^h4 ] -> [ 0, 1, 0, 0, 0, 0 ]; [ c, 1, 0, ^h4, ^h4 ] -> [ 0, 1, 0, 0, 0, 0 ]; end
61/83 AN1154 - application note appendix b: stimulus file tutor8xx.stl the tutor8xx.stl file consists of four sections: 1. parameter definitions: each of the m88 flash+psd control registers has an i/o address (offset from the csiop base address). the parameters make the stimulus file easier to read. 2. user-defined tasks: these are used to define and implement the microcontroller bus cycles. in each task, the timing of the control signals and address or data bus should follow that of the microcontroller, but they do not have to be exact; they just have to be to scale. the psd simulator will simulate a bus cycle every time a read , write , or psen task is called. 3. signal initialization: you must specify the initial logic level of all the input signals before simulation. the output signals that you want to simulate should be initialized to a high impedance state. 4. the stimulus inputs: here the stimulus inputs are needed to perform mcu read or write bus cycles to access the flash, eeprom, sram or i/o ports. inputs can also be generated to exercise the cpld functions. //title:tutor8xx.stl //function:simulation file for the m88x3fxx tutorial //designed by:dan harris //design date:6-23-98 //description:this file is intended to be used in the psdsilosiii environment as a // stimulus file for the m88x3fxx tutorial. the idea of this file is not // to show how the verilog-hdl language works, but rather the format of // a .stl file, and how it applies to this tutorial example. // the main parts of this file are: // * parameter declarations which make the file more readable // * read, write and "psen/" bus cycle tasks for the 80c31 // * an area where the user may wish to add to the file in order to // test more functions // * the actual stimulus of the design // ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++ // parameters declarations for the address offsets for the csiop address space // ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++ //port a parameter port_a_dir_reg='h0906,port_a_cntl_reg ='h0902; parameter port_a_dout_reg='h0904,port_a_din_reg ='h0900; parameter port_a_imc='h090a,port_a_drive_sel = 'h0908; parameter port_a_en_out='h090c; //port b
AN1154 - application note 62/83 parameter port_b_dir_reg='h0907,port_b_cntl_reg ='h0903; parameter port_b_dout_reg='h0905,port_b_din_reg ='h0901; parameter port_b_imc='h090b,port_b_drive_sel = 'h0909; parameter port_b_en_out='h090d; //port c parameter port_c_dir_reg='h0914,port_c_en_out ='h091a; parameter port_c_dout_reg='h0912,port_c_din_reg ='h0910; parameter port_c_imc='h0918,port_c_drive_sel = 'h0916; //port d parameter port_d_dir_reg='h0915,port_d_drive_sel ='h0917; parameter port_d_dout_reg='h0913,port_d_din_reg ='h0911; parameter port_d_en_out='h091b; //port ab omcs parameter port_ab_omc='h0920,port_ab_omc_mask = 'h0922; //port bc omcs parameter port_bc_omc='h0921,port_bc_omc_mask = 'h0923; //other control registers parameter flash_protect='h09c0,eeprom_protect = 'h09c2; parameter pmmr0_reg='h09b0,pmmr1_reg ='h09b2; parameter pmmr2_reg='h09b4,jtag_en = 'h09c4; parameter page_reg='h09e0,vm_reg ='h09e2; // ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++ // defining tasks to simulate 80c31 bus cycles (read, write and psen bus cycles). // note that the cycles are shortened for simulation purposes, but the functionality // remains the same. // ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++ //the "write task" implements the 80c31 write bus cycle task write; input [15:0] addr_bus; input [7:0] data_in;
63/83 AN1154 - application note begin #20 ale = 1;//latch the address lines #20 adio = addr_bus;//read the valid address (adio defined in .top file) #20 ale = 0;//ale inactive #20 adio[7:0] = data_in;//write operation #40 wr = 0;//write pulse #100 wr = 1;//write ends #10 adio[7:0] = z8;//z16 defined in .top file end endtask //the "read task" implements the 80c31 read bus cycle timing task read; input [15:0] addr_bus; begin #20 ale = 1;//latch the address lines #20 adio = addr_bus;//read the valid address #20 ale = 0;//ale inactive #20 adio[7:0] = z8;//float address bus (z8 defined in .top) #40 rd = 0;//read pulse #100 rd = 1;//read ends end endtask //the "psen task" implements the 80c31 psen program fetch bus cycle task psen; input [15:0] addr_bus; begin #20 ale = 1;//latch the address lines #20 adio = addr_bus;//set-up the right address #20 ale = 0;//ale inactive #20 adio[7:0] = z8;//float address bus #40 psen = 0;//read pulse #100 psen = 1;//read ends end
AN1154 - application note 64/83 endtask // ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++ // define some busses here to make the program easier to read. // ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++ //adrout is the latched address output on port a reg [4:0] adrout; reg addr_out4, addr_out3,addr_out2, addr_out1, addr_out0; assign {addr_out4, addr_out3, addr_out2, addr_out1, addr_out0} = adrout; reg [3:0] measured_value; reg measured_level3, measured_level2, measured_level1, measured_level0; assign {measured_level3, measured_level2, measured_level1, measured_level0} = measured_value; reg [3:0] desired_value; reg desired_level3, desired_level2, desired_level1, desired_level0; assign {desired_level3, desired_level2, desired_level1, desired_level0} = desired_value; reg [3:0] pga_data; reg pga_din3, pga_din2, pga_din1, pga_din0; assign {pga_din3, pga_din2, pga_din1, pga_din0} = pga_data; reg [2:0] cntrl; reg control2, control1, control0; assign {control2, control1, control0} = cntrl; // ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++ // stimulus starting point // // initialize all the i/o first. then proceed with the rest of the simulation.
65/83 AN1154 - application note // ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++ initial begin //initialize the signals first wr = 1; rd = 1; reset = 0;adio = 'h0000; ale = 0;psen = 1; adrout = z8; measured_value = 'h0; desired_value = 'h0; pga_data=z4;cntrl = z3; intrn = z1;start_conv = z1; trim = z1;boost = z1; jcen = 1; #100 reset = 1; // take the psd out of reset after 100ns //we are now ready to do some configuration of the psd //port a configuration //configure port a, pins pa4 to pa0 to output the latched address, and the rest //of the port will output control information in mcu i/o mode. //writing "1f" to the port a control register enables latched address output on //pins pa4 to pa0, and the rest of the port to output mcu i/o. write(port_a_cntl_reg, 'h1f); //writing "ff" to port a's direction register sets up port a pins to be outputs. write(port_a_dir_reg,'hff); //port b configuration //since there is no latched address output on port b, and its control register //defaults to mcu i/o mode output, only the direction register needs to be setup. //only pins pb3 to pb0 will be outputting data, and the rest will be receiving //input write(port_b_dir_reg,'h0f); //all of port c is output (with the exception of the vstby input write(port_c_dir_reg,'hfb);
AN1154 - application note 66/83 //there is only one output on port d (rtccs/), so the direction register is //setup as follows: write(port_d_dir_reg,'h04); //set up the mask registers so that only the desired portion of the omcs get //written. only the desired value (mcellab[7:4]), and begin (mcellbc7) can be //written to. write(port_ab_omc_mask, 'h0f); write(port_bc_omc_mask, 'h7f); //write the eeprom segment ees0, and the flash segment fs1 //then read the sram write('h0020,'h5a);//write 5a to ees0 write('h5a00,'ha5);//write a5 to fs1 read ('h07fe); //read the internal sram // wait, then initialize the gain to one and output the data on the pins // pb2 to pb0. #40 write(port_b_dout_reg,'h01); // assume a small value for the output of the adc since the gain is set // to one measured_value='h3; // load 5 into the desired value register write(port_ab_omc, 'h50); // take the state machine out of the idle state and generate the adc // chip select. #20 write(port_bc_omc, 'h80); // since the measured value is less than the desired one, the gain would // be boosted after the interrupt was generated (3 cycles after the start // of the state machine). the mcu should increment the gain by 1 at that // time. #400 write(port_b_dout_reg, 'h02); #10 $finish;
67/83 AN1154 - application note end initial begin // generate a 10 mhz system clock used by the state machine, etc. // note the time scale is set in the psdsoft.run file. clkin=0; forever #100 clkin=~clkin; end //stimulus ends here
AN1154 - application note 68/83 appendix c: list of m88 flash+psd simulation signals figure 61 gives a list of signals from the explorer that can be viewed using the data analyzer. this list is based on the tutor8xx.abl file, and predefined signals. the list will vary depending on the names in your .abl file, but most of the signals will be the same. figure 61. list of simulation signals any of the above signals can be dragged to the data analyzer window for viewing. once there, the signals can be made into buses. for more information on the explorer or data analyzer, see psdsilosiiis on-line help, and the psdsilosiii user manual . ai03198
69/83 AN1154 - application note table 3 contains all of the viewable predefined signal names, along with a brief description of each. the conventions used in the table are: n n represents a number n x represents a letter see the list above to determine which letters or numbers apply to the respective signal. table 3. table c1Cpredefined signal names and their descriptions signal/bus name description vm vm register adioh[15:8] address/data bus high byte adiol[7:0] address/data bus low byte ctrl_x port x control register data[7:0] non-multiplexed 8-bit data bus din_x port x data in register dirff_x port x direction register dout_x port x data out register drive_x port x drive register ecsdn external chip select output n ee_boot_oe eeprom output enable ee_power_down eeprom power down signal ee_protection[3:0] psd security and eeprom sector protection ee_ready_busy_n eeprom ready/busy signal ee_sdp_disable eeprom software data protection disable bit ee_sdp_enable eeprom software data protection enable bit ee_toggle eeprom toggle signal eesel_f eeprom final chip select enable_x enable to port x driver f_protection[7:0] flash sector protection register (read only) flash_oe flash output enable flash_polling flash data polling bit flash_ready_busy flash ready/busy signal flash_toggle flash toggle bit flsel_f flash final chip select jtag jtag enable register mask_mcab mask ab register outputs mask_mcbc mask bc register outputs mcellabn micro cell ab n output mcellabn_clk output micro cell ab n clock input
AN1154 - application note 70/83 mcellabn_pr output micro cell ab n preset input mcellabn_reg output micro cell ab n register input mcellabn_re output micro cell ab n reset input mcellbcn output micro cell bc n output mcellbcn_clk output micro cell bc n clock input mcellbcn_pr output micro cell bc n preset input mcellbcn_reg output micro cell bc n register input mcellbcn_re output micro cell bc n reset input nib_xn product term control port x[7:4] or x[3:0] input micro cell out_mcab[7:0] output registers for micro cell ab out_mcbc[7:0] output registers for micro cell bc pxn port x, pin n pxn_imc port x, input micro cell n pxn_oe port x, output enable n product term pdn power down signal pgr7_0 page register outputs pmmrn power management mode register n pseln port n peripheral select rd_bsy psd internal ready/busy status signal sram_oe sram output enable signal signal/bus name description
71/83 AN1154 - application note appendix d: design file for epm7064s (u2 of figure 2) -- title:8xx tutorial--discrete solution -- function:replacement for the programmable logic portions of the m88x3fxx -- designed by:dan harris -- design date:6/15/98 -- description:this design shows what chip and logic would be required to replace the -- programmable logic portions of the m8813f1x. this chip will be responsible -- for the following tasks: -- * latching the address generated by the 80c31 mcu. -- * decoding the address and generating internal/external chip selects. -- * storing control/status information in internal registers. -- * address translation for memory pageng. -- * interfacing to and controlling of the pga in the receiver circuit, and the adc -- rtc, sram, eeprom, flash, and mcu. -- * interfacing to a jtag-compatible port for isp. -- convention:the tilde (~) is used throughout this design to indicate active low signals. constant page_reg_addr = h"09e0"; constant vm_reg_addr = h"09e2"; constant mcu_io_out_addr = h"0902"; constant desired_reg_addr = h"0920"; constant gain_reg_addr = h"0901"; constant start_sig_addr = h"0921"; subdesign 8xxtutor ( -- the following signals are generated by the mcu (u1): a/d[7..0]: bidir;-- multiplexed address (lower byte)/data bus a[15..8]: input;-- upper byte of the addr bus rd~ : input;-- read strobe wr~ : input;-- write strobe ale : input;-- addr latch enable signal psen~ : input;-- program store enable -- system-level inputs: reset~ : input;-- system reset clock : input;-- system clock -- the following signals are generated for the mcu (u1): agc_interrupt~: output;-- interrupt the mcu when the desired and measured signal levels don't match
AN1154 - application note 72/83 trim : output;-- true when the measured level is greater than the desired one boost : output;-- opposite of trim -- the chip select output for the rtc (u5): rtc_cs~: output; -- this signals are to/from the adc (u7): start_conversn: output; -- indicates when the adc should start its analog-to- digital conversion adc_out[3..0]: input; -- the measured signal strength -- the bus is used to set the gain on the pga (part of u8) pga_din[2..0]: output; -- the following are outputs to the external memories: -- chip selects flash_cs~: output; eeprom_cs~: output; sram_cs~: output; -- output enables flash_oe~: output; eeprom_oe~: output; sram_oe~: output; -- upper address bits flash_a[16..14]: output;-- ms addr bits for the 128k flash - for segmentation eeprom_a[14..13]: output;-- ms addr bits for the 32k eeprom - for segmentation -- latched/demultiplexed address output addr_out[7..0]: output;-- outputs to the external memories -- control output for mcu i/o mode control[2..0]: output; ) variable a/d[7..0] : tri;-- needed to drive the data output onto the data bus la[7..0] : latch;-- must demux lower byte of addr page_reg[7..0]: dffe;-- page register vm_reg[7..0]: dffe; -- used for memory mapping in combined memory space mode desired_reg[3..0]: dffe;-- register to store the desired signal level (set by the mcu) gain_reg[2..0]: dffe; -- register to store the gain level (set by the mcu) begin_comparrison: dffe; -- takes state machine out of idle state (s0)
73/83 AN1154 - application note cntrl_port_reg[2..0]: dffe;-- mcu i/o mode control register addr[15..0]: node;-- demultiplexed addr fs[7..0] : node;-- flash segment enable signals ees[3..0] : node; -- eeprom segment enable signals swap : node; -- bit 7 of the page register enable_data_half: node;-- bit 6 of the page register measured[3..0]: node;-- output from the adc desired[3..0]: node;-- input from the mcu meqd : node;-- true when the measured value equals the desired one sm : machine with states (s0, s1, s2, s3); begin -- right now, there is nothing to output to the mcu on the a/d lines a/d[] = gnd; -- latch in the addr[] la[] = a/d[]; la[].ena = ale; addr[7..0] = la[]; addr[15..8] = a[]; addr_out[] = la[]; begin_comparrison = a/d7; begin_comparrison.clk = clock; begin_comparrison.clrn = reset~; begin_comparrison.ena = !wr~ & (addr[] == start_sig_addr); desired_reg[] = a/d[7..4]; desired_reg[].clk = clock; desired_reg[].clrn = reset~; desired_reg[].ena = !wr~ & (addr[] == desired_reg_addr); gain_reg[] = a/d[2..0]; gain_reg[].clk = clock; gain_reg[].clrn = reset~; gain_reg[].ena = !wr~ & (addr[] == gain_reg_addr); cntrl_port_reg[] = a/d[2..0]; cntrl_port_reg[].clk = clock; cntrl_port_reg[].clrn = reset~; cntrl_port_reg[].ena = !wr~ & (addr[] == mcu_io_out_addr); page_reg[] = a/d[];
AN1154 - application note 74/83 page_reg[].clk = clock; page_reg[].clrn = reset~; page_reg[].ena = !wr~ & (addr[] == page_reg_addr); vm_reg[] = a/d[]; vm_reg[].clk = clock; vm_reg[].clrn = reset~; vm_reg[].ena = !wr~ & (addr[] == vm_reg_addr); measured[] = adc_out[]; desired[] = desired_reg[]; pga_din[] = gain_reg[]; control[] = cntrl_port_reg[]; -- memory section swap = page_reg7; enable_data_half = page_reg6; fs0 = ((addr[] >= h"8000") & (addr[] <= h"bfff") & (page_reg[] == 3) & !swap) # ((addr[] >= h"0000") & (addr[] <= h"3fff") & swap); fs1 = (addr[] >= h"4000") & (addr[] <= h"7fff"); fs2 = (addr[] >= h"8000") & (addr[] <= h"bfff") & (page_reg[] == 0); fs3 = (addr[] >= h"c000") & (addr[] <= h"ffff") & (page_reg[] == 0); fs4 = (addr[] >= h"8000") & (addr[] <= h"bfff") & (page_reg[] == 1); fs5 = (addr[] >= h"c000") & (addr[] <= h"ffff") & (page_reg[] == 1); fs6 = (addr[] >= h"8000") & (addr[] <= h"bfff") & (page_reg[] == 2); fs7 = (addr[] >= h"c000") & (addr[] <= h"ffff") & (page_reg[] == 2); ees0 = ((addr[] >= h"0000") & (addr[] <= h"1fff") & !swap) # ((addr[] >= h"8000") & (addr[] <= h"9fff") & swap & !enable_data_half); ees1 = ((addr[] >= h"2000") & (addr[] <= h"3fff") & !swap) # ((addr[] >= h"a000") & (addr[] <= h"bfff") & swap & !enable_data_half); ees2 = (addr[] >= h"c000") & (addr[] <= h"dfff") & swap & enable_data_half; ees3 = (addr[] >= h"e000") & (addr[] <= h"ffff") & swap & enable_data_half; -- flash upper 3 and eeprom upper 2 address bit encoding flash_a16 = fs7 # fs6 # fs5 # fs4; flash_a15 = fs7 # fs6 # fs3 # fs2; flash_a14 = fs7 # fs5 # fs3 # fs1; eeprom_a14 = ees3 # ees2; eeprom_a13 = ees3 # ees1; -- chip selects and output enables
75/83 AN1154 - application note -- sram has highest priority, followed by eeprom, and then flash !flash_cs~ = (fs0 # fs1 # fs2 # fs3 # fs4 # fs5 # fs6 # fs7) & (eeprom_cs~ # sram_cs~); !eeprom_cs~ = (ees0 # ees1 # ees2 # ees3) & sram_cs~; !sram_cs~ = ((addr[] >= h"0100") & (addr[] <= h"08ff")); !rtc_cs~ = ((addr[] >= h"0a00") & (addr[] <= h"0a1f")); !sram_oe~ = !(!rd~ # (!psen~ & vm_reg0)); !eeprom_oe~ = !((!psen~ & vm_reg1) # (vm_reg3 & !rd~)); !flash_oe~ = !((!psen~ & vm_reg2) # (vm_reg4 & !rd~)); -- comparator i/o trim = (measured[] > desired[]); meqd = (measured[] == desired[]); boost = !trim & !meqd; -- state machine sm.clk = clock; sm.reset = !reset~; case sm is when s0 => start_conversn = gnd; agc_interrupt~ = vcc; if (begin_comparrison) then sm = s1; else sm = s0; end if; when s1 => start_conversn = vcc; sm = s2; when s2 => start_conversn = gnd; sm = s3; when s3 => !agc_interrupt~ = trim # boost;-- interrupt when measured not equal to desired sm = s0; end case; end;
AN1154 - application note 76/83 appendix e: comparing the discrete and integrated solutions this appendix compares the two circuits of figure 2 and figure 3 in the following categories: n cost n average current usage n board space usage n time to market (only the major ics are compared here.) cost the 150 ns m8813f1x in the plcc package can be purchased at a significantly lower price than the total cost of the individual eeprom, flash, sram, and cpld devices. average current usage the m88x3fxx would typically use 4.29 ma according to the example of m88x3fxx typical power calculation at v cc = 5.0 v in the ac and dc parameters sections of the m88 flash+psd data sheet . if we take the total average current of the devices in the discrete solution, we get 32.4 ma (with the epm7064s not in turbo mode). this shows that the discrete solution uses 755% more current than the pld. board space usage the m8813f1x in the plcc package takes up 400 mm 2 . the chips that make up the discrete solution take up a combined 1493 mm 2 . that equates to 373% more board space. (all calculations have been based on plcc packages.) this calculation does not reflect the extra board space, complexity, and noise associated with routing the signals in the discrete solution. time to market the time to market will be reduced significantly for many reasons: n the integrated psd solution involves one complex integrated circuit, not four. n there are templates and predefined routines that, when used in conjunction with our user-friendly psdsoft, help you with every step of your design process. n issues related to concurrent memory, memory mapping, and mcu assisted isp are simplified. n c code is generated for you. n the jtag interface is one of the greatest benefits and time savers. it allows you to program, configure, and test the entire psd, and leave it soldered to the board the whole time. n there are just fewer places to go wrong, and fewer things to debug when you have this level of integration.
77/83 AN1154 - application note appendix f: system memory map and uart isp introduction a system memory map was developed for this tutorial to take full advantage of the memory available in the m8813f1x, and to expand beyond the 64 kbyte address space limitation of the 8031 mcu. this memory map facilitates the downloading of firmware from a host computer to the flash memory in the psd using the 8031 uart. the 8031 boots from the psd eeprom, concurrently downloads to psd flash memory, and then 8031 execution jumps from eeprom to flash memory. after this jump, the eeprom in the boot area address space is replaced with flash memory by a special register within the psd (the vm register). after that, the entire flash memory is available to the 8031. this system memory map also allows the concurrent downloading of boot code into the psd eeprom while executing code out of psd flash memory. this is not possible in non-psd systems that use prom for boot code. the total memory available to the 8031 as defined in this system is: n 128 kbytes flash n 16 kbytes eeprom for boot code n 16 kbytes eeprom for data storage n 2 kbytes battery-backed sram (in addition to the 256 bytes sram resident on the 8031) system memory map the system memory map is shown in figure 62, figure 63, figure 64, and figure 65. the labels fsx and eesx are the names of internal memory segments within the m8813f1x device. fsx represents 16 kbyte flash segments, eesx represents 8 kbyte eeprom segments. in this design, paging is used because the system contains more memory than the 8031 can address linearly. the m8813f1x facilitates paging by using a page register, which the 8031 can access. because paging is used, a common memory area is needed for firmware routines that must be accessible regardless of what page the mcu is executing from. this common area resides in the lower half of each memory page in program space (shown in figure 62, figure 63, figure 64, and figure 65). it should contain routines that handle initialization, interrupts, implement page switching, and drive physical devices. it is also used to keep critical data space items available at all times. for example, in this design, the psd control registers, i/o, and system sram for the stack and global variables are available on any memory page (see figure 62, figure 63, figure 64, and figure 65). there are two fundamental modes of operation: one is boot/download mode, and the other is normal operation. figure 62, figure 63, figure 64, and figure 65 show the memory map during the transition from boot/download mode to normal operation mode. figure 16 represents the memory map at power-on (boot). the system boots up from eeprom, and then facilitate a download to the main flash memory (if needed) using the 8031 uart. at this point, all of the psd flash memory is in the 8031 data space and all of the eeprom is in the 8031 program space. this is due to the mcu bus configuration that was performed in step 2 of the section entitled psdsoft configuration (on page 20), and shown in figure 16. this step of the configuration automatically sets the vm register to 12h. please refer to the m88 flash+psd data sheet for information on the vm register settings. it is very important to note that the psd configuration utility initialises the vm register (located in the csiop space at offset e2h), and that it can only be changed by the mcu after it has booted. after the flash has been programmed or validated, the flash memory is moved from the 8031 data space to the
AN1154 - application note 78/83 8031 program space by the mcu writing 06h to the vm register (while still executing out of psd eeprom). figure 62 represents the memory map after the flash memory has been moved to the program space. this is an intermediate step that is a result of writing to the vm register. next, the 8031 execution jumps from psd eeprom to psd flash memory. while executing from psd flash memory, the 8031 sets a bit in the psd page register that we call swap. the eeprom that the mcu booted from, during power-up, is replaced with flash memory that contains application vectors and code, as shown in figure 64. the transition between the two maps of figure 63 and figure 64 is under the control of the 8031 by setting the swap bit inside the psd (defined in the psdabel, tutor8xx.abl , file). again, the state of the memory map, shown in figure 64, is an intermediate step. individual bits within the 8-bit psd page register may be used for functions other than memory page definition. for example, in this tutorial, two of the eight psd page register bits are use to define four memory pages, and one of the page register bits is used as the swap bit, as described above. finally, while executing from the psd flash memory, the 8031 must write 0ch to the vm register in the psd to move the psd eeprom from the 8031 program space to the 8031 data space. this finalizes the memory map, as shown in figure 65. now, all 128 kbytes of psd flash memory are in the program space, with 32 kbytes in a common area and 96 kbytes spread across three memory pages. also, the eeprom is now in the data space, and is accessible from any memory page. notice that two more psd eeprom segments (ees2 and ees3) appear in figure 65. these two segments are for general data use while the other two eeprom segments (ees0 and ees1) contain the 8031 power-on boot code. now that the system memory map looks like that of figure 65, another feature becomes available. besides the mechanisms mentioned, there is one more memory mapping control bit used in this tutorial design. this bit, enable_data_half, is another psd page register bit used to protect the boot code in ees0 and ees1 from inadvertent writes. at the same time, it enables the other half of the eeprom (ees2 and ees3) to be accessed for general data. for example, to update the boot code in ees0 and ees1 with new code downloaded over the uart, the 8031 would leave enable_data_half at logic zero, perform the update by writing to ees0 and ees1, then set enable_data_half to logic one. now the new boot code is inaccessible (protected while not booting), and the data half of eeprom is accessible. figure 62. system memory map for 8031-m8813f1x, boot/download power-up (vm register = 12h) ai03300 ffff 0000 4000 8000 c000 ffff 0000 4000 8000 c000 1000 2000 ees0 ees1 system ram & i/o system ram & i/o system ram & i/o system ram & i/o fs1 fs1 fs1 fs1 fs2 fs3 fs4 fs5 fs7 fs6 fs0 program space (psen\) page x data space (rd\) page 0 page 1 page 2 page 3 common memory across all data pages execute from here nothing mapped nothing mapped nothing mapped nothing mapped nothing mapped nothing mapped
79/83 AN1154 - application note figure 63. system mem map for 8031-m8813f1x, move flash to program space write 06h to the vm register figure 64. system memory map for 8031-m8813f1x, swap boot eeprom with flash segment set swap bit = 1 ai03301 ffff 0000 4000 8000 c000 system ram & i/o fs1 fs1 fs1 fs1 fs2 fs3 fs4 fs5 fs7 fs6 fs0 program space page 0 page 1 page 2 page 3 common memory across all program pages 2000 data space page x ffff 0000 4000 8000 c000 1000 ees0 ees1 ees0 ees1 ees0 ees1 ees0 ees1 nothing mapped execute from here nothing mapped ai03302 ffff 0000 4000 8000 c000 system ram & i/o fs1 fs1 fs1 fs1 fs3 fs5 fs7 program space page 0 page 1 page 2 page 3 common memory across all program pages data space page x ffff 0000 4000 8000 c000 1000 ees0 ees1 ees0 ees1 ees0 ees1 ees0 ees1 fs0fs0fs0fs0 execute from here nothing mapped nothing mapped
AN1154 - application note 80/83 figure 65. final sys mem map for 8031-m8813f1x, move eeprom to data space write 0ch to the vm register code partitioning in the flash memory pages ultimately, the mcu will be executing from flash memory since the eeprom is used for boot-up and isp in this design. let us assume that we have 128 kbytes of program space in flash memory, as shown in figure 65. the 128 kbytes of code resides in four areas: 32 kbytes in the common area (fs0 and fs1, accessible from any page), 32 kbytes on page zero (fs2 and fs3), 32 kbytes on page one (fs4 and fs5), and 32 kbytes on page two (fs6 and fs7). if the 8031 never leaves page zero while executing, it can access 64 kbytes of flash memory in fs0 through fs3 as well as all of the sram and i/o. if the 8031 execution jumps to flash memory on pages one or two from a call on the upper half of page zero (fs2 or fs3), care must be taken to leave a path to return to page zero again. however, if the call to page one or two is from a routine in the lower half of page zero (the common area, fs0 or fs1), there is no problem returning from the call. when placing code in the flash memory on the upper half of pages zero, one, or two, the software designer must break tasks into logical groups. these groups should not need to access code frequently on other pages. (most software can be split in this manner and is a result of a good modular design.) since system sram is available on any page, firmware routines that reside on different pages may pass data using global variables or the stack. the designer can create page-switching algorithms to jump between tasks on different pages. there are many ways to implement a paging scheme: one method involves the use of a table that contains addresses and page numbers of all program tasks, which may be called from page to page. the table and algorithms must reside in the portion of flash memory that is located in the common area. this provides a very clean paging solution, which may be implemented using a high-level compiler. (the compiler from keil supports this directly, and creates the tables for you.) the only penalty when using this method is the overhead experienced when switching from one page to another. for this tutorial design, five different files from an mcu cross-compiler and linker are used to program the nvm sections of the m8813f1x. these are dummy files with no code in them, but are present to illustrate the merging of mcu firmware with the psd configuration during the address translate operation. if this were a real design, the file common.hex would contain all of the common functions and interrupt vectors, and would be programmed into fs0/fs1. three more files from the mcu linker, page_0.hex, page_1.hex, and page_2.hex would contain the partitioned code described above. as such, these three files would be programmed into segments fs2/fs3, fs4/fs5, and fs6/fs7, respectively. finally, the file boot.hex , ai03303 ffff 0000 4000 8000 c000 system ram & i/o fs1 fs1 fs1 fs1 fs3 fs5 fs7 program space page 0 page 1 page 2 page 3 common memory across all program pages data space page x ffff 0000 4000 8000 c000 1000 fs0fs0fs0fs0 ees0 ees1 fs2 fs4 fs6 ees2 ees3 nothing mapped nothing mapped
81/83 AN1154 - application note containing the power-up boot code and programming algorithms for flash memory, would be programmed into ees0/ees1. start-up sequences, uart downloads let us assume that a pc or lap-top is to be used as a host to download firmware to this embedded system over an rs-232 uart channel (instead of jtag). these download actions can program the main flash memory for the very first time; can update the main flash after it has been programmed once; or can update the boot code after being programmed for the first time by a device programmer or jtag link. there are six valid boot-up arrangements (labelled respectively: a, b, c, d, e and f) that must be handled by the system at power-up (reset). the default setting of the vm register at power-up places the main flash memory in the data space and the eeprom in the program space. please refer to the memory maps in figure 62, figure 63, figure 64, and figure 65. a. rs-232 cable not attached, main flash valid 8031 action: boot from ees0/ees1 run a checksum on the flash memory check the uart for a pending host download request of main flash (figure 62) set a bit in the psd vm register to put main flash into program space (figure 63) set the swap bit in psd, which swaps ees0/ees1 with fs0 (figure 64) set a bit in the psd vm register to put the eeprom into data space (figure 65) now, the system is in normal operating mode. more 8031 action: check the uart for a host download request of boot memory set the enable_data_half bit in the psd if no boot download request exists normal application code can now be executed from main flash memory. b. rs-232 cable attached, main flash valid, no download demands from host action: same as step "a.", above. c. rs-232 cable attached, main flash valid, download of main flash is demanded by host 8031 action: boots from ees0/ees1 run a checksum on the flash memory check the uart for a pending host download request of main flash (figure 62) program the main flash memory with data from the uart set a bit in the psd vm register to put main flash into program space (figure 63) set the swap bit in psd, which swaps ees0/ees1 with fs0 (figure 64) set a bit in the psd vm register to put the eeprom into data space (figure 65) now, the system is in normal operating mode. more 8031 action: check the uart for a host download request of boot memory set the enable_data_half bit in the psd if no boot download request exists normal application code can now be executed from main flash memory.
AN1154 - application note 82/83 d. rs-232 cable not attached, main flash is blank or invalid 8031 action: boot from ees0/ees1 run a checksum on the flash memory check the uart for a pending host download request of main flash (figure 62) wait until any uart traffic is present (figure 62) e. rs-232 cable attached, main flash is blank or invalid 8031 action: boot from ees0/ees1 run a checksum on the flash memory check the uart for a pending host download request of main flash (figure 62) program the main flash memory with data from the uart set a bit in the psd vm register to put main flash into program space (figure 63) set the swap bit in psd, which swaps ees0/ees1 with fs0 (figure 64) set a bit in the psd vm register to put the eeprom into data space (figure 65) now, the system is in normal operating mode. more 8031 action: check the uart for a host download request of boot memory set the enable_data_half bit in the psd if no boot download request exists normal application code can now be executed from main flash memory. f. rs-232 cable attached, main flash is valid, system requests a download of boot memory 8031 action: boot from ees0/ees1 run a checksum on the flash memory check the uart for a pending host download request of main flash (figure 62) set a bit in the psd vm register to put main flash into program space (figure 63) set the swap bit in psd, which swaps ees0/ees1 with fs0 (figure 64) set a bit in the psd vm register to put the eeprom into data space (figure 65) now, the system is in normal operating mode. more 8031 action: check the uart for a host download request of boot memory program the eeprom boot memory in ees0 and ees1 with data from the uart run a checksum on ees0 and ees1 set the enable_data_half bit in the psd to protect the boot code in ees0 and ees1 from inadvertent writes enable data access of ees2 and ees3 normal application code can now be executed from main flash memory. for of any of these host uart download options, it is assumed that the normal boot (ees0/ees1) area is programmed the very first time by a device programmer before the psd is installed on the circuit card or by the jtag interface while the psd is in-system.
83/83 AN1154 - application note for current information on m88 flash+psd products, please consult our pages on the world wide web: www.st.com/flashpsd if you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail addresses: apps.flashpsd@st.com (for application support) ask.memory@st.com (for general enquiries) please remember to include your name, company, location, telephone number and fax number. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. ? 2000 stmicroelectronics - all rights reserved the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - sing apore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com

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